Metal-oxide-silicon ("MOS") devices in general and MOS memory devices in particular can suffer performance and reliability degradation from a number of sources. For example, all MOS devices can suffer from hot carrier degradation. Memory devices such as electrically programmable read only memory ("EEPROM") devices, electrically erasable and programmable read only memory ("EPROM") devices also can suffer from charge loss, which affects their ability to reliably store data. Static random access memory ("SRAM") devices can suffer from trapped mobile carriers that affect the stability of associated polysilicon pull-up resistors, which renders accurate data readout difficult.
Before examining the nature of these problems and such solutions as are known in the art, it is helpful to briefly review the fabrication of MOS devices, including memory devices.
MOS integrated circuits typically provide many MOS devices fabricated on a substrate, with electrical isolation between adjacent devices provided by a field oxide layer. Typically a semiconductor layer comprising active source and drain regions for the MOS devices is covered by gate oxide regions, which regions are in turn covered by first polysilicon gate deposits (commonly called "polysilicon 1" or "poly 1" level gates). In charge storage memory devices such as EEPROMs and EPROMs, second polysilicon gate regions are also formed (known as "polysilicon 2" or "poly 2" level gates), overlying the first gate regions. An inter-gate oxide separates the two gate levels.
An interlayer dielectric ("ILD") such as boron phosphorous silicate glass ("BPSG") is then formed to insulate the gate regions from an overlying first level of conductive traces (commonly called "metal 1").
An inter-metal-oxide ("IMO") layer is then provided to insulate the layers thus described from an overlying second level of conductive metal traces (commonly called "metal 2"). The IMO layer typically includes a spin-on-glass ("SOG") layer that may be organic. The SOG layer is applied as a liquid to planarize or even-out the topography, primarily the valleys created by the underlying metal traces.
Finally, an outermost passivation layer is formed to protect the underlying integrated circuit from external sources of degradation. This outermost or "topside" layer typically includes a plasma enhanced chemical vapor deposition ("PECVD") of silane or tetra-ethyl-ortho-silicade ("TEOS") oxide.
Although the outermost passivation layer provides some protection against external sources of degradation, the underlying MOS devices are also susceptible to internal degradation. Sources of internal degradation include charge buildup, charge trapping, and the relatively large electric fields induced by backend processing.
Some sources of internal degradation have been successfully dealt with. For example a detrimental field-inversion can result from hydrogen in a nitride passivation layer migrating downward into a carbon-bearing layer such as an organic SOG layer. The resultant H--C interaction forms positive charges (or species) that can impress a voltage in excess of a substrate threshold voltage across the isolation channel oxide. The resultant isolation breakdown can invert the substrate beneath the affected oxide layer, thus permitting the flow of undesired inter-device leakage current. Hot carrier degradation can also result from such interaction.
The above-referenced U.S. Pat. No. 5,057,897 discloses the use of a silicon-enriched oxide beneath the passivation layer to reduce such parasitic leakage. Preferably the silicon-enriched oxide is formed within the IMO layer on either side of the SOG. Dangling bonds associated with the silicon-enriched oxide trap or neutralize the charge, minimizing the formation of parasitic transistors and leakage paths due to field inversion.
However due to a variety of mechanisms, undesired charges can be impressed on any of the dielectric layers, which charges need not originate from any interaction between a nitride passivation layer and an organic SOG layer. The above referenced application Ser. No. 775,085 discloses the use of one or more amorphous silicon layers to further trap or neutralize such charges that could otherwise contribute to inversion of isolation field oxides. Such amorphous silicon layers may be formed on either side of an SOG layer, and/or on either side of the BPSG layer. As such, the region wherein charges are trapped or generated preferably lies above the amorphous-silicon layer(s).
Hot carrier reliability affects all MOS devices, and can be important in MOS memory devices. Hot carrier lifetime depends upon device structure, doping densities, gate oxide thicknesses, the strength of applied fields, and the like. Long hot carrier lifetime is desired (i.e., months or years), but as noted fabrication process steps including backend steps can shorten hot carrier lifetime, with the result that MOS memory devices suffer performance and reliability degradation.
As MOS device sizes shrink and packing densities increase, there is an increase in the magnitude of the electric field to which the MOS devices are exposed. Unfortunately these increased field intensities create ionization regions wherein valence bonds are too easily broken. Hot carriers injected into these regions can readily damage the gate oxide-substrate interface by breaking these bonds. The result is that holes and electrons become trapped within the gate oxide. These trapped charges can undesirably alter and render less stable the MOS device characteristics including threshold voltage, conductance, and drive current levels. In addition, the increased use of plasma-assisted etching and deposition processing can further degrade hot electron reliability, primarily affecting hot carrier trapping.
It is known to use lightly doped drain structures to somewhat improve hot carrier lifetimes by reducing the electric fields to which a MOS device is subjected. However backend high voltage plasma deposition or etching processes, and the presence of SOG layers can still degrade hot carrier lifetime. The above-referenced application Ser. No. 07/794,922 discloses the use of silicon-enriched layers to provide a measure of internal passivation from backend induced hot carrier degradation. The silicon-enriched layers are disposed beneath any layer that may be the source of moisture, carbon and hydrogen, for example beneath each of the BPSG, SOG and passivation layers.
Needless to say, reliable data retention and data readout is all important in MOS memory devices. Unfortunately the performance and reliability of memory devices is subject to degradation from many sources, including those described above. For example, in EEPROMs and EPROMs, charged impurity ions can penetrate the BPSG layer, where they are attracted to the floating gate used to store data, thus degrading data retention. Memory data retention can also be adversely affected by effects remote from the floating gate, due to mechanisms not entirely understood at present. Although providing increased phosphorus content in the ILD is known to retard charge loss, further measures are still needed to produce EEPROMs and EPROMs that can reliably store data for long periods of time. Similarly, further measures are needed to protect SRAM data readout from migrating species induced instability of the pull-up resistors.
While the above-described patent and two pending patent applications disclose solutions to some of the problems affecting MOS device performance, further solutions are desired, especially with respect to MOS memory devices. What is needed is a method and structure for internally passivating MOS devices including memory devices against backend-processing induced degradation. Such method and structure should suppress charge loss in EPROM/EEPROM devices, and enhance stability of polysilicon load resistors in SRAM devices. The present invention discloses such methods and structures.